This invention relates to programmable logic devices, and more particularly to a new architecture for an erasable programmable logic device ("EPLD") using a multiplexer-based global interconnect array ("GIA") which allows for EPLDs with higher speed and the ability to realize more complex functions than previously possible.
Another aspect of this invention relates to user programmable logic devices. More particularly, the invention relates to a macrocell in which product terms can be allocated between an OR gate and registered logic, and in which product terms can be summed together with product terms from an adjacent macrocell.
As shown by commonly-assigned U.S. Pat. No. 4,871,930 ("Wong"), which is hereby incorporated by reference in its entirety, and the references cited therein, programmable logic devices ("PLDs") are well known. As described in Wong, a major obstacle in increasing the logic density in previously known PLDs was the size of the single global interconnection array which increased as the square of the number of output functions. This obstacle was overcome to a large extent by the use of a programmable interconnect array ("PIA") disclosed in Wong. In a PLD using a PIA, a single global interconnection array using erasable programmable read-only memory ("EPROM") cells was used to route signals to and from logic array blocks ("LABs") which contained logic elements, macrocells, and a local interconnection array.
The architecture using PIAs and LABs disclosed in Wong produced a generation of successful PLDs available commercially from Altera Corporation of San Jose, Calif. Yet, to meet ever increasing technological demands, PLDs have been constantly increasing in both size and complexity. In particular, to achieve higher logic density, more logic elements have been incorporated into PLDs and this has necessitated increasing the size of the PIA.
However, a significant amount of the power used in PLDs is consumed in the programmable elements of the PIA, and a major speed limitation is capacitive loading in the programmable elements of the PIA. Increasing the size of the PIA, therefore, leads undesirably to higher power consumption and reduction in speed.
In view of the foregoing, it would be desirable to be able to provide a PLD architecture in which power consumption is reduced by eliminating programmable elements from the PIA.
It would further be desirable to be able to provide a PLD architecture in which speed is increased by reducing capacitive loading on the interconnect array.
It is an object of this invention to provide a PLD architecture in which power consumption is reduced by eliminating programmable elements from the PIA.
It is a further object of this invention to provide a PLD architecture in which speed is increased by reducing capacitive loading on the interconnect array.
User programmable logic devices provide flexibility in digital logic design by allowing a designer to implement logic functions through a sum-of-products architecture typically composed of an array of AND gates connected to an array of OR gates. The outputs from the AND gates are referred to as product terms. The output of each OR gate provides the sum of the input product terms.
Typically, a macrocell receives a number of product terms as inputs. Some of the product terms are input to the OR gate. The output of the OR gate then is typically fed to a register which stores the result. Some devices feature additional combinatorial logic associated with the register (registered logic). This logic typically allows inputs to the register to be inverted or combined with the output of the register or with the product terms not used by the OR gate.
In a typical macrocell, the number of product terms that can be ORed together is limited to the number of product terms that are input to the macrocell. Another type of conventional macrocell has the ability to share its OR function with a second macrocell, but in such a macrocell use of the OR function by the second macrocell precludes use of the remaining logic in the macrocell. Also, in a conventional macrocell having the ability to steer product terms to either an OR gate or to registered logic, use of the OR function must be sacrificed when product terms are steered to the registered logic.
In view of the foregoing, it is an object of this invention to provide a macrocell which supports summing of an arbitrary number of product terms by daisy chaining the OR gates of an arbitrary number of macrocells. It is a further object of this invention so to provide a macrocell in which use of its OR function by another macrocell does not prevent the use of the remaining logic elements of the macrocell. It is another object of this invention to provide a macrocell in which product terms may be steered to the register logic without sacrificing use of the OR function.